DSP IP cuts power and area in embedded SOCs

Synopsys expands its DesignWare ARC IP portfolio with DSPs that afford greater design flexibility to meet power, performance, and area demands. Joining the higher-performance 512-bit VPX5, the 128-bit VPX2 and 256-bit VPX3 achieve up to two-thirds lower power and area.

The VPX2 and VPX3 are available in single- and dual-core configurations and use the same very long instruction word (VLIW)/single instruction, multiple data (SIMD) architecture as the 512-bit VPX5. Their smaller vector length allows the ARC VPX DSP family to address a broader range of embedded designs, including IoT, AI, automotive, and voice/language processing.

Each VPX core contains a scalar execution unit and multiple vector units that handle 8-bit, 16-bit, and 32-bit SIMD computations. The DSPs also support half, single, and double precision floating-point formats, and up to three floating-point pipelines are available in each core.

Aimed at automotive applications, ARC VPXxFS processors integrate hardware safety features, such as error correction code (ECC) protection for memories and interfaces, safety monitors, and lockstep mechanisms. These safety-enhanced processors help designers achieve the most stringent levels of ISO 26262 ASIL B, ASIL C and ASIL D functional safety compliance.

DesignWare ARC VPX2 and VPX3 processor IP will be available to lead customers in Q4 2021. VPX2FS and VPX3FS processor IP is scheduled to be available to lead customers in Q1 2022.

DesignWare ARC VPX product page


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