A software-defined radio (SDR) uses a general-purpose computer processor to perform aspects of digital signal processing in place of analog circuit hardware. This allows for greater flexibility in application, processing ability, and dynamic range often at a lower cost relative to dedicated circuitry. When compared to a fully-analog radio, an SDR replaces some analog circuitry with equivalent software implementations, although some analog components will be required.
The primary example of analog components required for any SDR is the transmission or reception amplifier circuit that interfaces with the radio frequency antenna. An important part of any radio system is a mixer whose purpose is to shift the frequency of a signal, either up or down in frequency—a process referred to as heterodyning. SDRs use digital mixers that represent signals using complex numbers allowing them a significant advantage over their analog equivalents—they are able to perform frequency shifting of a signal down to DC while an analog mixer is only able to shift a signal to a lower frequency.
Typically, SDRs have higher bandwidths around their center frequency, allowing a larger slice of the radio spectrum to be monitored and tuning over a broader range without needing to retune. Put another way, this means that SDRs are often capable of offering high instantaneous bandwidths over a wide tuning range spanning from DC to over 18 GHz. Due to the combination of these two high-performance-radio attributes, the radio and signal processing hardware required to support frequency tuning may vary.
It is important to note that depending on design and frequency range, frequency mixing and tuning can be implemented at any point along the signal chain, including in digital or analog. This article discusses the specific mechanisms available for tuning various frequencies, including direct sampling, in phase quadrature (IQ) mixing, and super heterodyne mixing.
What’s frequency mechanics?
This document uses the term frequency mechanics to refer to the process by which a high-frequency signal is shifted down in frequency to a range appropriate for sampling by an analog-to-digital converter (ADC) as well as the subsequent frequency translations that may occur once the signal is digitized. A specific radio path must be selected based on the frequency of the signal—different radio paths are optimized for different frequency ranges. Within each radio chain, the frequency may be mixed by analog converters, effectively shifting the frequency up or down.
Similarly, a digital signal may also be shifted, either within the converter, or within the FPGA. Depending on the frequency range selected, different methods of sampling and conversion are used. In brief, this article discusses the specific tuning mechanics, along with the relevant frequency mechanics for each mode of operation.
|Method||Analog tuning components||Frequency tuning location|
|IQ||Mixer||Hardware followed by software|
|Super-heterodyne||IF downconverter, possibly second mixer||Hardware|
Direct sampling refers to sampling (or sending) signals directly from the antenna with minimal or no analog components in between. In other words, a chunk of the radio frequency (RF) signal is sampled, digitized, and passed on to software for processing. Although simple, constraints of this method include noise and the availability of high-speed sampling hardware and clocks. Since a large spread of the RF spectrum is sampled, multi-band applications are possible without having to retune.
The ability to tune into different frequencies depends on the sampling rate of the ADC or digital-to-analog-converter (DAC) when transmitting. Commercially available converter devices can sample up to 3GSPS (giga samples per second) allowing a large amount of data to be digitized in a short amount of time. These sample rates allow for sampling data across multiple frequency bands, including many commercial cellular frequency bands.
SDRs are often operated as transceivers—devices capable of both transmitting and receiving—and the direct sampling chain is one among several chains possible on wideband SDRs. The direct sampling chain is automatically chosen when using frequencies below those supported by the analog down converter.
The external antenna is connected to the SDR through switches and amplifiers, however, note that no analog components for frequency conversion are used. All resampling and frequency conversion is implemented in software and the analog circuitry is used solely for signal conditioning—filtering—and amplification.
Figure 1 Direct sampling refers to transmission of signals directly from the antenna with minimal or no analog components in between. Source: Per Vices
When the SDR is operated as a transmitter, data is generated by the user application and is received by the FPGA as samples. The qSFP+ ports send the digitized data over a serial link to the FPGA, where resampling and frequency mixing occur in the digital domain. It then passes through the FPGA-based interpolation routine followed by FPGA-based digital up conversion—using the numerically-controlled oscillator (NCO). Any user applied frequency shifting occurs after interpolation, prior to sending the data to the DAC, as shown in Figure 1. The frequency shifted digital data is then converted by the DAC into an analog signal, which generates image frequencies as part of the conversion process. The now-analog signal passes through anti-imaging filters, through the radio front end amplifiers, and then out to the radio antenna.
Baseband transmission mechanics
As the samples move through the various components in the SDR, the frequencies and bandwidths change. Now that we have a good understanding of our circuitry, let’s look at what happens to the signal at each of these steps.
The lower half of Figure 1 shows three waveforms that we might be looking to transmit. Prior to the samples getting generated, the user defines a sample rate (labelled A). The sample rate serves to specify the user bandwidth; an interval [-A/2, A/2] which is centered around 0 Hz. Since these waveforms will be offset by the NCO frequency at a later stage, the initial sine waves in some cases may have a negative frequency—like the black signal in the diagram. Once generated, the samples will be sent to the SDR via a serial link for further processing. It is important to note that not all of the samples in the user bandwidth will be transmitted—it will become clear later (see the yellow signal in the diagram above).
After generating user samples, the next step is performing interpolation to obtain a larger bandwidth. This new bandwidth specifies a larger interval—also centered around 0 Hz—that is defined by the sample rate of the device (325 MSPS for Crimson TNG, 1 GSPS for Cyan). The user bandwidth is always smaller than the conversion bandwidth. Interpolating the samples to a larger bandwidth is crucial for the next stage where the digital up-conversion takes place.
After interpolating the signal to the conversion bandwidth of the device, the FPGA can proceed to upconvert the samples. Recall that up-conversion simply shifts all frequencies up by a fixed amount—the frequency of the NCO. Both Crimson TNG and Cyan have CORDIC digital mixers that are capable of both up-conversion and down-conversion (DUC, DDC). Up-conversion is accomplished by mixing the user samples with a local oscillator found in the FPGA (set to NCO frequency). This causes the frequency of all our signals to increase. Using the larger conversion bandwidth that we obtained from interpolation ensures that we can capture more of our mixing products.
In some cases (see the signal in yellow), mixing our generated signal with the NCO frequency results in a frequency that does not lie within the user bandwidth. Here the mixing product will still have an image that is rotated to fit within our capture bandwidth (see the dotted line in yellow). For baseband signals, negative frequency components are discarded and hence this image is not relevant and is ignored.
The DAC then converts the signals to their analog form. Despite how good modern-day DACs perform, Nyquist images of the original signals will exist; at each multiple of our conversion bandwidth, we are likely to see images of the signal at their corresponding offsets. Anti-imaging filters are used to suppress the images that would typically show up at higher Nyquist zones—multiples of the conversion bandwidth. The final analog signal can now be transmitted via the antenna.
Direct IQ or in-phase quadrature sampling is a variant of direct sampling where a received RF signal is split into two components, separated by 90 degrees in phase. Two ADC channels—or DAC channels for transmission—are used to sample these phase-shifted signals. The process for direct IQ reception is described below.
Figure 2 Direct IQ receiver, a variant of direct sampling, employs two channels to sample phase-shifted signals. Source: Per Vices
The first section on the left side of Figure 2 shows three pure sine waves and their images as they are picked up by the antenna. A variable attenuator attenuates frequencies outside the band of interest. The following stage—the IQ modulator—combines the I and Q components to form the RF signal. This process shifts all frequencies down by an amount determined by the local oscillator (LO). Note that this is an analog process.
An analog anti-aliasing filter aims to restrict the incoming signal to only those that fall in the converter’s domain. This is important because the ADC has a finite operating range of frequency that is limited by its sampling rate. The converter bandwidth specifies a large interval centered around 0 Hz that is defined by the sample rate of the device (325 MSPS for Crimson TNG, 1 GSPS for Cyan). The ADC converts the incoming signals into a digital form.
At this point, the converted bandwidth is large for digital processing. To prepare for decimation, the samples are digitally down-converted. This decreases the frequency of all the signals by the NCO frequency set on the FPGA. The Crimson TNG and Cyan have CORDIC digital mixers capable of both DUC and DDC. Down-conversion is accomplished by mixing the received samples with a local oscillator found in the FPGA—set to what is referred to as the NCO frequency. Note that after this takes place, some of the frequencies—like the one shown in red—might be negative.
Prior to the samples being received, the user defines a sample rate (labelled B). The sample rate in turn specifies the user bandwidth, an interval [-B/2, B/2] which is centered around 0 Hz. Decimation ensures that all the incoming signals fall within the user bandwidth.
A heterodyne receiver mixes the received RF signal (f1) with a reference signal from a local oscillator (f2) to produce two signals at intermediate frequencies of (f1 ± f2). A superheterodyne—shortened to super-het—receiver’s intermediate frequency (IF) is chosen such that it is easier to process with analog electronics and is consequently above normal human-audible frequencies (hence the prefix of “super”).
A super-het receiver is shown in Figure 3. Note that only a receiver is shown for simplicity—the equivalent transmission circuit will use similar components with the signal flow reversed. The associated analog stages are chosen automatically when the user selects a working frequency in the super-het range. A super-het receiver first down-converts the received RF using an analog mixer. This is achieved by a suitable separate circuit labelled a “LOgen board” in Figure 3. Using high-frequency analog mixing in this manner produces what are referred to as beat frequencies or multiples of the IF. Analog filters are required before digitization.
Figure 3 The superheterodyne receiver’s IF is chosen such that it’s easier to process with analog electronics. Source: Per Vices
A second stage of down conversion is implemented using the IQ modulator followed by anti-imaging filters to remove conversion products generated by the high-frequency mixing process. The IF is now digitized and can be further mixed using digital mixers before decimation and ultimate use in software.
Depending on the working frequency, a wideband SDR selects from among the available analog circuitry. When working with baseband frequencies or direct sampling, no analog mixing is possible, and frequency is limited by circuit clock speed. When working with higher frequencies, analog mixer circuits are required, and the number of analog mixing stages again depends on frequency. Working in the GHz range typically requires a super-het analog circuit and typically two analog mixing circuits in order to lower signal frequency to the working range of the digital components, such as ADCs or DACs.
Using a single device for wideband tuning requires an understanding of the trade-offs of various methods. Examples include signal artifacts caused by analog mixing or the cost of high-speed conversion devices if analog mixing is not desired. It is important to work with vendors that have experience developing for wideband operation and that have the capability to modify their products to meet the specific requirements associated with a given project. It is best to select a vendor based on their available products, specifications, applications supported, and a discussion around their capabilities.